This application claims the priority of Korean Patent Application No. 2003-0056009, filed on Aug. 13, 2003, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, to semiconductor capacitor structures and methods for manufacturing the same.
2. Description of the Related Art
The driving capability of semiconductor devices such as dynamic random access memory (DRAM) is determined by the capacitance of capacitors, which generally consist of a capacitor dielectric layer sandwiched between two capacitor electrodes. The capacitance is largely determined by the total surface area of the electrodes and the distance between the electrodes as determined by the thickness of the capacitor dielectric layer. Therefore, many attempts have been made to increase the capacitance by increasing the effective surface area of the capacitor electrodes.
Unfortunately, however, as semiconductor devices become more highly integrated, the area allocated for forming capacitors within the devices typically becomes reduced. In other words, as integration density increases, the width of capacitors narrows, and it becomes more difficult to obtain the desired capacitance levels.
Fabrication technologies have been developed to increase the height of a capacitor electrode or storage node, to increase the effective surface area thereof and to retain a desirable cell capacitance of the unit cell. For example, a storage node can be formed in a concave or cylindrical shape having a height of more than 1 μm.
Unfortunately, as the height of the storage node increases, the area of the storage node decreases due to the increasingly sloped profile of the storage node formation hole. This leads to an increasingly unstable and unreliable capacitor structure. In particular, a phenomenon such as “stiction” or “leaning” of storage nodes can occur, especially if the height of the storage nodes is above 15,000 nm. These problems are illustrated, for example, FIGS. 1A and 1B. The stiction phenomenon is typically caused by the surface tension of a liquid drop remaining between the ends of adjacent storage node electrodes during a drying process performed before a cleaning process. The leaning phenomenon is caused by a difference in the coefficients of thermal expansion (CTE) between an etch stop nitride layer and storage nodes during thermal cycling.
To improve the stability of the capacitor structures, the width of the bottom portion of the storage node should be increased and a sufficient distance between the adjacent storage nodes need to be ensured. In this respect, a minimum space critical dimension (CD) has been defined to represent a desired distance between adjacent storage nodes in a diagonal direction. Increasing this minimum space CD reduces the likelihood that the storage nodes will not fall in the event that there is leaning of storage nodes.
However, as illustrated in FIGS. 2A–2B, obtaining the sufficient distance between the storage nodes has become more difficult as the device sizes become scaled down. In particular, it is difficult to increase the width W of the bottom portion of the storage nodes without decreasing the distance B between the adjacent storage nodes. In particular, as the width W of the storage node bottom portion increases to W′ by an amount A (See FIG. 2B), the distance B between the storage nodes inevitably decreases to B′ by a proportionate amount.
It is, therefore, difficult to form a reliable capacitor structure without decreasing the storage node bottom portion while avoiding conventional problems such as stiction or leaning of storage nodes.